1. Field of the Invention
The present invention relates a semiconductor device and a method of manufacturing the device, and more specifically, to a semiconductor device with a field-effect transistor having an improved current drivability and a method of manufacturing such a device.
2. Description of the Background Art
As an example of a conventional semiconductor device, a semiconductor device having a field-effect transistor will be described below in relation to the drawings. As seen from FIG. 21, a pair of source/drain diffusion regions 105a, 105b positioned at a prescribed interval are formed on a surface of a silicon substrate 101. On the region of silicon substrate 101 located between the pair of source/drain diffusion regions 105a, 105b a gate electrode 104a is formed, with a gate oxide film 103a formed therebetween. Gates sidewall oxide films 106a, 106b are formed, one on each side surface of gate electrode 104a. A source/drain electrode 107a is formed on the surface of a source/drain diffusion region 105a. Moreover, a source/drain electrode 107b is formed on the surface of a source/drain diffusion region 105b. A gate upper electrode 107c is formed on gate electrode 104a.
In the above-described manner, the main portion of a semiconductor device having a field-effect transistor is formed on silicon substrate 101. The field-effect transistor is electrically isolated from another field-effect transistor (not shown) by an element isolating oxide film 102 formed in silicon substrate 101.
Now, an example of a method of manufacturing the above-described semiconductor device will be described with reference to the drawings. As shown in FIG. 22, element isolating oxide film 102 is formed on the surface of silicon substrate 101 by trench isolation method. Then, as shown in FIG. 23, a silicon oxide film 103 is formed on the surface of silicon substrate 101 using thermal oxidation method or the like. On silicon oxide film 103, a polysilicon film 104 is formed by CVD (Chemical Vapor Deposition) method or the like. On polysilicon film 104, a photo resist (not shown) is provided, and a photo resist pattern 108 is formed by the use of an appropriate photolithography.
Now, as shown in FIG. 24, using photo resist pattern 108 as a mask, polysilicon film 104 and silicon oxide film 103 are anisotropically etched to form gate electrode 104a and gate oxide film 103a. Thereafter, photo resist pattern 108 is removed.
Next, as shown in FIG. 25, using gate electrode 104a as a mask, an impurity of a prescribed conductivity type is implanted into a surface of silicon substrate 101 using ion implantation method to form a pair of source/drain diffusion region 105a, 105b, respectively. Then, as shown in FIG. 26, a silicon oxide film 106 is formed on silicon substrate 101 to cover gate electrode 104a by CVD method.
Next, as shown in FIG. 27, silicon oxide film 106 is etched anisotropically to form gate sidewall oxide films 106a, 106b, each of which is formed respectively on each side surface of gate electrode 104a. Then, as shown in FIG. 28, silicon is epitaxially grown selectively on gate electrode 104a and source/drain diffusion regions 105a, 105b by epitaxial growth method to form gate upper electrode 107c and source/drain electrodes 107a, 107b, respectively. In this manner, the main portion of the semiconductor device having the field-effect transistor shown in FIG. 21 is completed.
In recent years, miniaturization of field-effect transistors has been promoted in order to keep up with the higher degrees of integration achieved in semiconductor devices. As a field-effect transistor is miniaturized, its gate length is reduced, which leads to a lower threshold voltage, causing the so-called short-channel effect leading to the incorrect operation of the field-effect transistor. Conventionally, in order to prevent the short-channel effect in such a field-effect transistor, the film thickness of the gate oxide film has been reduced, or the depth of a source/drain region (or the depth of junction) has been made smaller. With a smaller depth of the source/drain region, however, the electrical resistance (sheet resistance) in the source/drain region cannot be sufficiently lowered, and the amount of the current flowing through the source/drain region becomes smaller. As a result, problems such as lowering of the current drivability in the field-effect transistor arise, leading to a decreased operation speed. Conventionally, in order to prevent such problems, conductive layers, i.e. source/drain electrodes 107a, 107b, are formed on the surfaces of the source/drain regions to reduce the sheet resistance of the source/drain regions, thereby ensuring the current drivability of the field-effect transistor.
In the above-described semiconductor device, however, source/drain electrodes 107a, 107b were not formed on the portions (extension portions E) located beneath gate sidewall oxide films 106a, 106b on the surfaces of source/drain diffusion regions 105a, 105b. Therefore, it was impossible sufficiently to reduce the sheet resistance of source/drain diffusion regions 105a, 105b in extension portions E. Consequently, further improvement in the current drivability of the field-effect transistor was limited.